Renato Perez Ribas

Dados pessoais

Lattes
Grupos de Pesquisa
Genealogia Acadêmica

Nacionalidade: Brasileira
Grande área de atuação: Engenharias
Área de atuação: Engenharia Elétrica

Publicações

Total: 210

Área temática ASJC

Percentual das publicações classificadas

HS Ciências da Saúde
LS Ciências da Vida
MU Multidisciplinar
PS Ciências Físicas
SH Ciências Sociais e Humanidades

Categoria ASJC

Categorias ASJC mais frequentes

Nome	Vínculo	Grande área de atuação	Área de atuação
Nome	Vínculo	Grande área de atuação	Área de atuação
Airam Teresa Zago Romcy SAUSEN		Ciências Exatas e da Terra	Matemática
Dante Augusto Couto BARONE		Ciências Exatas e da Terra	Ciência da Computação
Leomar Soares Da Rosa JUNIOR		Ciências Exatas e da Terra	Ciência da Computação

Figura 1

Número de publicações por ano e por tipo

Todas as publicações do perfil

Figura 2

Categorias ASJC mais frequentes por ano

A cor dos pontos identifica a categoria predominante

Figura 3

Mapa de calor das categorias ASJC por ano

Frequências absolutas; cores mais escuras indicam mais publicações. Todas as categorias ASJC e anos disponíveis, sem aplicar os filtros da página.

Escala: 0 → 9

Mapa de calor das categorias ASJC por ano
Categoria ASJC	1989	1990	1991	1992	1993	1994	1995	1996	1997	1998	1999	2000	2001	2002	2003	2004	2005	2006	2007	2008	2009	2010	2011	2012	2013	2014	2015	2016	2017	2018	2019	2020	2021	2022	2023	2024	2025
1708 · Hardware and Architecture	2	5	0	1	0	1	1	0	1	1	1	2	2	3	1	3	0	4	4	2	6	0	5	3	9	1	6	0	0	1	1	0	0	0	2	0	0
2208 · Electrical and Electronic Engineering	0	2	2	0	1	0	1	5	1	4	2	1	2	1	1	3	1	2	1	1	4	5	2	1	6	3	3	1	1	0	0	0	0	0	0	2	0
1703 · Computational Theory and Mathematics	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0	0	0	0	3	1	1	1	0	3	0	0	0	2	0	0	0	0	0	0
1706 · Computer Science Applications	0	0	0	0	0	0	0	0	0	0	1	1	1	2	0	0	1	0	1	0	0	1	0	0	0	0	2	0	2	0	0	0	1	0	0	0	0
1701 · Computer Science (miscellaneous)	0	0	0	0	0	0	0	0	0	0	0	0	1	1	0	0	0	0	2	1	1	0	0	0	0	3	1	0	0	0	0	0	0	1	0	0	0
2209 · Industrial and Manufacturing Engineering	0	0	0	0	0	0	0	0	1	0	1	1	0	0	2	0	0	0	0	1	0	0	0	1	0	1	0	2	0	0	0	0	0	0	0	0	0
1704 · Computer Graphics and Computer-Aided Design	0	0	0	0	0	0	0	0	0	0	1	0	2	0	0	1	0	0	0	0	0	0	0	0	0	0	0	1	0	1	1	0	0	1	0	0	0
2609 · Logic	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	1	0	0	1	0	0	2	0	0	1	0	0	0	0	0	0	0
2614 · Theoretical Computer Science	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	1	0	1	0	0	0	1	0	0	0	0	0	0	0
3304 · Education	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	1	0	0	0	0	0	0	0
1702 · Artificial Intelligence	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	2	0	0	0	0	0	0	1	0	0	0	0	0	0	0
2210 · Mechanical Engineering	0	0	0	0	0	0	0	0	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
2504 · Electronic; Optical and Magnetic Materials	0	0	1	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
2607 · Discrete Mathematics and Combinatorics	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	1
1508 · Process Chemistry and Technology	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
1707 · Computer Vision and Pattern Recognition	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0
2501 · Materials Science (miscellaneous)	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
2601 · Mathematics (miscellaneous)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0

Ano	Tipo	Registro	Área temática e categoria ASJC
	Tipo de Publicação	Registro	Área temática e categoria ASJC
2012	Trabalho em evento	Read polarity once functions Vinicius CALLEGARO; Mayler G A MARTINS; Renato Perez RIBAS; Andre Inacio REIS International Workshop on Logic and Synthesis	PS Logic
2012	Trabalho em evento	K-cuts and KL-cuts on netlist representations for local remapping Lucas MACHADO; Osvaldo Martinello JR; Renato Perez RIBAS; Andre Inacio REIS International Workshop on Logic and Synthesis	PS Hardware and Architecture
2012	Trabalho em evento	Functional composition paradigm and applications Mayler G A MARTINS; Vinicius CALLEGARO; Lucas MACHADO; Renato Perez RIBAS; Andre Inacio REIS International Workshop on Logic and Synthesis	PS Theoretical Computer Science
2012	Trabalho em evento	Design-oriented delay model for CMOS inverter Marranghello Felipe S; Reis Andre I; Renato Perez RIBAS 2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI) DOI 10.1109/SBCCI.2012.6344424 ISBN 9781467326087	PS Electrical and Electronic Engineering
2012	Trabalho em evento	NSP kernel finder - A methodology to find and to build non-series-parallel transistor arrangements Possani Vinicius N; Marques Felipe S; Da Rosa Junior Leomar S; Callegaro VINICIUS; Reis Andre I et al 2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI) DOI 10.1109/SBCCI.2012.6344452 ISBN 9781467326087	PS Hardware and Architecture
2012	Artigo em periódico	Design of CMOS logic gates with enhanced robustness against aging degradation Butzen P F; Vinicius Dal BEM; Reis A I; Renato Perez RIBAS Microelectronics and Reliability DOI 10.1016/j.microrel.2012.06.092 ISSN 0026-2714	PS Hardware and Architecture
2011	Trabalho em evento	Constructive AIG optimization considering input weights Tiago FIGUEIRÓ; Renato Perez RIBAS; Andre Inacio REIS International Symposium on Quality Electronic Design DOI 10.1109/ISQED.2011.5770816	PS Artificial Intelligence
2011	Trabalho em evento	Constructive AIG optimization through functional composition Tiago FIGUEIRÓ; Renato Perez RIBAS; Andre Inacio REIS Workshop on Exploiting Regularity in the Design of IPs; Architectures and Platforms	PS Artificial Intelligence
2011	Trabalho em evento	Transistor sizing analysis of regular fabrics Felipe MARRANGHELLO; Vinicius Dal BEM; Andre Inacio REIS; Renato Perez RIBAS; Francesc MOLL Workshop on Exploiting Regularity in the Design of IPs; Architectures and Platforms	PS Hardware and Architecture
2011	Trabalho em evento	SYNAPTIC project: regularity applied to enhance manufacturability and yield at several abstraction levels Martin ELHOJ; Andre Inacio REIS; Renato Perez RIBAS; Fabrizio FERRANDI; Christian PILATO et al Workshop on Exploiting Regularity in the Design of IPs; Architectures and Platforms	PS Hardware and Architecture
2011	Trabalho em evento	Efficient method to compute minimum decision chains of Boolean functions Mayler G A MARTINS; Vinicius CALLEGARO; Renato Perez RIBAS; Andre Inacio REIS ACM Great Lakes Symposium on VLSI DOI 10.1145/1973009.1973098	PS Computational Theory and Mathematics
2011	Trabalho em evento	Ring Oscillators for Functional and Delay Test of Latches and Flip-Flops Renato Perez RIBAS; Yuyang SUN; Andre IVANOV; André I REIS Symposium on Integrated Circuits and Systems Design DOI 10.1145/2020876.2020893 ISBN 9781450308281	PS Electrical and Electronic Engineering
2011	Trabalho em evento	Area impact analysis of via-configurable regular fabric for digital integrated circuit design Dal Bem VINÍCIUS; Butzen Paulo F; Klock Carlos E; Callegaro VINICIUS; Reis André I et al the 24th symposium DOI 10.1145/2020876.2020901 ISBN 9781450308281	PS Hardware and Architecture
2011	Trabalho em evento	Transistor sizing in lithography-aware regular fabrics Felipe MARRANGHELLO; Vinicius Dal BEM; André I REIS; Francesc MOLL; Renato Perez RIBAS Symposium on Integrated Circuits and Systems Design DOI 10.1145/2020876.2020900 ISBN 9781450308281	PS Hardware and Architecture
2011	Trabalho em evento	Self-checking test circuits for latches and flip-flops Renato Perez RIBAS; Sun YUYANG; Reis Andre I; Andre IVANOV 2011 IEEE 17th International OnLine Testing Symposium (IOLTS 2011) DOI 10.1109/IOLTS.2011.5993846 ISBN 9781457710537	PS Electrical and Electronic Engineering
2011	Artigo em periódico	Contributions to the evaluation of ensembles of combinational logic gates Renato Perez RIBAS; Simone BAVARESCO; Nivea SCHUCH; Marcelo Soares LUBASZEWSKI; André I REIS Microelectronics (Luton) (Cessou em 1978. Cont. ISSN 0959-8324 Microelectronics Journal) DOI 10.1016/j.mejo.2010.11.012 ISSN 0026-2692	PS Hardware and Architecture
2010	Trabalho em evento	KL-Cuts: A new approach for logic synthesis targeting multiple output blocks Martinello OSVALDO; Felipe S MARQUES; Renato Perez RIBAS; Reis Andre I 2010 Design; Automation & Test in Europe Conference & Exhibition (DATE 2010) DOI 10.1109/DATE.2010.5456946 ISBN 9783981080162	PS Computational Theory and Mathematics
2010	Trabalho em evento	SwitchCraft: a framework for transistor network design Vinicius CALLEGARO; Felipe S MARQUES; Carlos KLOCK; Leomar Da Rosa JR; Renato Perez RIBAS et al Symposium on Integrated Circuits and Systems Design ISBN 9781450301527	PS Electrical and Electronic Engineering
2010	Trabalho em evento	Improvements on the detection of false paths by using unateness and satisfiability Marques Felipe S; Martinello OSVALDO; Renato Perez RIBAS; Reis André I the 23rd symposium DOI 10.1145/1854153.1854201 ISBN 9781450301527	PS Computational Theory and Mathematics
2010	Trabalho em evento	Boolean factoring with multi-objective goals Mayler G A MARTINS; Leomar Da Rosa JR; Anders B RASMUSSEN; Renato Perez RIBAS; André I REIS International Conference on Computer Design (ICCD) DOI 10.1109/ICCD.2010.5647772 ISBN 9781424489367	PS Computational Theory and Mathematics
2010	Artigo em periódico	Leakage Analysis Considering the Effect of Intra-Cell Wire Resistance for Nanoscaled CMOS Circuits Paulo BUTZEN; André Inácio REIS; Renato Perez RIBAS Journal of Low Power Electronics (Print) DOI 10.1166/jolpe.2010.1070 ISSN 1546-1998	PS Electrical and Electronic Engineering
2010	Artigo em periódico	Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits Paulo BUTZEN; Leomar Da Rosa JR; Erasmo J D Chiappetta FILHO; André Inácio REIS; Renato Perez RIBAS MICROELECTRONICS JOURNAL DOI 10.1016/j.mejo.2010.03.003 ISSN 0026-2692	PS Electrical and Electronic Engineering
2010	Artigo em periódico	Transistor Network Restructuring Against NBTI Degradation Paulo BUTZEN; Vinicius Dal BEM; André Inácio REIS; Renato Perez RIBAS Microelectronics and Reliability DOI 10.1016/j.microrel.2010.07.140 ISSN 0026-2714	PS Electrical and Electronic Engineering
2010	Artigo em periódico	Gate Delay Variability Model for Parametric Yield Improvement in Nanometer CMOS Technology Da Silva Digeorgia N; André Inácio REIS; Renato Perez RIBAS Microelectronics and Reliability DOI 10.1016/j.microrel.2010.07.071 ISSN 0026-2714	PS Electrical and Electronic Engineering
2010	Artigo em periódico	Karma: um ambiente para o aprendizado de síntese de funções Booleanas Carlos KLOCK; Renato Perez RIBAS; André Inácio REIS Revista Brasileira de Informática na Educação ISSN 1414-5685	PS Computer Science Applications

2012 Trabalho em evento

PS Logic

Read polarity once functions

International Workshop on Logic and Synthesis

Vinicius CALLEGARO; Mayler G A MARTINS; Renato Perez RIBAS; Andre Inacio REIS

2012 Trabalho em evento

PS Hardware and Architecture

K-cuts and KL-cuts on netlist representations for local remapping

International Workshop on Logic and Synthesis

Lucas MACHADO; Osvaldo Martinello JR; Renato Perez RIBAS; Andre Inacio REIS

2012 Trabalho em evento

PS Theoretical Computer Science

Functional composition paradigm and applications

International Workshop on Logic and Synthesis

Mayler G A MARTINS; Vinicius CALLEGARO; Lucas MACHADO; Renato Perez RIBAS; Andre Inacio REIS

2012 Trabalho em evento

PS Electrical and Electronic Engineering

Design-oriented delay model for CMOS inverter

2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)

Marranghello Felipe S; Reis Andre I; Renato Perez RIBAS

DOI ISBN 9781467326087

2012 Trabalho em evento

PS Hardware and Architecture

NSP kernel finder - A methodology to find and to build non-series-parallel transistor arrangements

2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)

Possani Vinicius N; Marques Felipe S; Da Rosa Junior Leomar S; Callegaro VINICIUS; Reis Andre I et al

DOI ISBN 9781467326087

2012 Artigo em periódico

PS Hardware and Architecture

Design of CMOS logic gates with enhanced robustness against aging degradation

Microelectronics and Reliability

Butzen P F; Vinicius Dal BEM; Reis A I; Renato Perez RIBAS

DOI ISSN 0026-2714

2011 Trabalho em evento

PS Artificial Intelligence

Constructive AIG optimization considering input weights

International Symposium on Quality Electronic Design

Tiago FIGUEIRÓ; Renato Perez RIBAS; Andre Inacio REIS

DOI

2011 Trabalho em evento

PS Artificial Intelligence

Constructive AIG optimization through functional composition

Workshop on Exploiting Regularity in the Design of IPs; Architectures and Platforms

Tiago FIGUEIRÓ; Renato Perez RIBAS; Andre Inacio REIS

2011 Trabalho em evento

PS Hardware and Architecture

Transistor sizing analysis of regular fabrics

Workshop on Exploiting Regularity in the Design of IPs; Architectures and Platforms

Felipe MARRANGHELLO; Vinicius Dal BEM; Andre Inacio REIS; Renato Perez RIBAS; Francesc MOLL

2011 Trabalho em evento

PS Hardware and Architecture

SYNAPTIC project: regularity applied to enhance manufacturability and yield at several abstraction levels

Workshop on Exploiting Regularity in the Design of IPs; Architectures and Platforms

Martin ELHOJ; Andre Inacio REIS; Renato Perez RIBAS; Fabrizio FERRANDI; Christian PILATO et al

2011 Trabalho em evento

PS Computational Theory and Mathematics

Efficient method to compute minimum decision chains of Boolean functions

ACM Great Lakes Symposium on VLSI

Mayler G A MARTINS; Vinicius CALLEGARO; Renato Perez RIBAS; Andre Inacio REIS

DOI

2011 Trabalho em evento

PS Electrical and Electronic Engineering

Ring Oscillators for Functional and Delay Test of Latches and Flip-Flops

Symposium on Integrated Circuits and Systems Design

Renato Perez RIBAS; Yuyang SUN; Andre IVANOV; André I REIS

DOI ISBN 9781450308281

2011 Trabalho em evento

PS Hardware and Architecture

Area impact analysis of via-configurable regular fabric for digital integrated circuit design

the 24th symposium

Dal Bem VINÍCIUS; Butzen Paulo F; Klock Carlos E; Callegaro VINICIUS; Reis André I et al

DOI ISBN 9781450308281

2011 Trabalho em evento

PS Hardware and Architecture

Transistor sizing in lithography-aware regular fabrics

Symposium on Integrated Circuits and Systems Design

Felipe MARRANGHELLO; Vinicius Dal BEM; André I REIS; Francesc MOLL; Renato Perez RIBAS

DOI ISBN 9781450308281

2011 Trabalho em evento

PS Electrical and Electronic Engineering

Self-checking test circuits for latches and flip-flops

2011 IEEE 17th International OnLine Testing Symposium (IOLTS 2011)

Renato Perez RIBAS; Sun YUYANG; Reis Andre I; Andre IVANOV

DOI ISBN 9781457710537

2011 Artigo em periódico

PS Hardware and Architecture

Contributions to the evaluation of ensembles of combinational logic gates

Microelectronics (Luton) (Cessou em 1978. Cont. ISSN 0959-8324 Microelectronics Journal)

Renato Perez RIBAS; Simone BAVARESCO; Nivea SCHUCH; Marcelo Soares LUBASZEWSKI; André I REIS

DOI ISSN 0026-2692

2010 Trabalho em evento

PS Computational Theory and Mathematics

KL-Cuts: A new approach for logic synthesis targeting multiple output blocks

2010 Design; Automation & Test in Europe Conference & Exhibition (DATE 2010)

Martinello OSVALDO; Felipe S MARQUES; Renato Perez RIBAS; Reis Andre I

DOI ISBN 9783981080162

2010 Trabalho em evento

PS Electrical and Electronic Engineering

SwitchCraft: a framework for transistor network design

Symposium on Integrated Circuits and Systems Design

Vinicius CALLEGARO; Felipe S MARQUES; Carlos KLOCK; Leomar Da Rosa JR; Renato Perez RIBAS et al

ISBN 9781450301527

2010 Trabalho em evento

PS Computational Theory and Mathematics

Improvements on the detection of false paths by using unateness and satisfiability

the 23rd symposium

Marques Felipe S; Martinello OSVALDO; Renato Perez RIBAS; Reis André I

DOI ISBN 9781450301527

2010 Trabalho em evento

PS Computational Theory and Mathematics

Boolean factoring with multi-objective goals

International Conference on Computer Design (ICCD)

Mayler G A MARTINS; Leomar Da Rosa JR; Anders B RASMUSSEN; Renato Perez RIBAS; André I REIS

DOI ISBN 9781424489367

2010 Artigo em periódico

PS Electrical and Electronic Engineering

Leakage Analysis Considering the Effect of Intra-Cell Wire Resistance for Nanoscaled CMOS Circuits

Journal of Low Power Electronics (Print)

Paulo BUTZEN; André Inácio REIS; Renato Perez RIBAS

DOI ISSN 1546-1998

2010 Artigo em periódico

PS Electrical and Electronic Engineering

Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits

MICROELECTRONICS JOURNAL

Paulo BUTZEN; Leomar Da Rosa JR; Erasmo J D Chiappetta FILHO; André Inácio REIS; Renato Perez RIBAS

DOI ISSN 0026-2692

2010 Artigo em periódico

PS Electrical and Electronic Engineering

Transistor Network Restructuring Against NBTI Degradation

Microelectronics and Reliability

Paulo BUTZEN; Vinicius Dal BEM; André Inácio REIS; Renato Perez RIBAS

DOI ISSN 0026-2714

2010 Artigo em periódico

PS Electrical and Electronic Engineering

Gate Delay Variability Model for Parametric Yield Improvement in Nanometer CMOS Technology

Microelectronics and Reliability

Da Silva Digeorgia N; André Inácio REIS; Renato Perez RIBAS

DOI ISSN 0026-2714

2010 Artigo em periódico

PS Computer Science Applications

Karma: um ambiente para o aprendizado de síntese de funções Booleanas

Revista Brasileira de Informática na Educação

Carlos KLOCK; Renato Perez RIBAS; André Inácio REIS

ISSN 1414-5685