Renato Perez Ribas

Dados pessoais

Lattes
Grupos de Pesquisa
Genealogia Acadêmica

Nacionalidade: Brasileira
Grande área de atuação: Engenharias
Área de atuação: Engenharia Elétrica

Publicações

Total: 210

Área temática ASJC

Percentual das publicações classificadas

HS Ciências da Saúde
LS Ciências da Vida
MU Multidisciplinar
PS Ciências Físicas
SH Ciências Sociais e Humanidades

Categoria ASJC

Categorias ASJC mais frequentes

Nome	Vínculo	Grande área de atuação	Área de atuação
Nome	Vínculo	Grande área de atuação	Área de atuação
Airam Teresa Zago Romcy SAUSEN		Ciências Exatas e da Terra	Matemática
Dante Augusto Couto BARONE		Ciências Exatas e da Terra	Ciência da Computação
Leomar Soares Da Rosa JUNIOR		Ciências Exatas e da Terra	Ciência da Computação

Figura 1

Número de publicações por ano e por tipo

Todas as publicações do perfil

Figura 2

Categorias ASJC mais frequentes por ano

A cor dos pontos identifica a categoria predominante

Figura 3

Mapa de calor das categorias ASJC por ano

Frequências absolutas; cores mais escuras indicam mais publicações. Todas as categorias ASJC e anos disponíveis, sem aplicar os filtros da página.

Escala: 0 → 9

Mapa de calor das categorias ASJC por ano
Categoria ASJC	1989	1990	1991	1992	1993	1994	1995	1996	1997	1998	1999	2000	2001	2002	2003	2004	2005	2006	2007	2008	2009	2010	2011	2012	2013	2014	2015	2016	2017	2018	2019	2020	2021	2022	2023	2024	2025
1708 · Hardware and Architecture	2	5	0	1	0	1	1	0	1	1	1	2	2	3	1	3	0	4	4	2	6	0	5	3	9	1	6	0	0	1	1	0	0	0	2	0	0
2208 · Electrical and Electronic Engineering	0	2	2	0	1	0	1	5	1	4	2	1	2	1	1	3	1	2	1	1	4	5	2	1	6	3	3	1	1	0	0	0	0	0	0	2	0
1703 · Computational Theory and Mathematics	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0	0	0	0	3	1	1	1	0	3	0	0	0	2	0	0	0	0	0	0
1706 · Computer Science Applications	0	0	0	0	0	0	0	0	0	0	1	1	1	2	0	0	1	0	1	0	0	1	0	0	0	0	2	0	2	0	0	0	1	0	0	0	0
1701 · Computer Science (miscellaneous)	0	0	0	0	0	0	0	0	0	0	0	0	1	1	0	0	0	0	2	1	1	0	0	0	0	3	1	0	0	0	0	0	0	1	0	0	0
2209 · Industrial and Manufacturing Engineering	0	0	0	0	0	0	0	0	1	0	1	1	0	0	2	0	0	0	0	1	0	0	0	1	0	1	0	2	0	0	0	0	0	0	0	0	0
1704 · Computer Graphics and Computer-Aided Design	0	0	0	0	0	0	0	0	0	0	1	0	2	0	0	1	0	0	0	0	0	0	0	0	0	0	0	1	0	1	1	0	0	1	0	0	0
2609 · Logic	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	1	0	0	1	0	0	2	0	0	1	0	0	0	0	0	0	0
2614 · Theoretical Computer Science	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	1	0	1	0	0	0	1	0	0	0	0	0	0	0
3304 · Education	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	1	0	0	0	0	0	0	0
1702 · Artificial Intelligence	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	2	0	0	0	0	0	0	1	0	0	0	0	0	0	0
2210 · Mechanical Engineering	0	0	0	0	0	0	0	0	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
2504 · Electronic; Optical and Magnetic Materials	0	0	1	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
2607 · Discrete Mathematics and Combinatorics	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	1
1508 · Process Chemistry and Technology	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
1707 · Computer Vision and Pattern Recognition	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0
2501 · Materials Science (miscellaneous)	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
2601 · Mathematics (miscellaneous)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0

Ano	Tipo	Registro	Área temática e categoria ASJC
	Tipo de Publicação	Registro	Área temática e categoria ASJC
2025	Livro	Divirta-se com 21 jogos lógicos no mesmo tabuleiro: Volume 1 Renato Perez RIBAS — ISBN 9786561440547	PS Discrete Mathematics and Combinatorics
2024	Trabalho em evento	Extending Multilevel ALS to Design ATMRs Ammes GABRIEL; Manske Guilherme B; Butzen Paulo F; Reis André I; Renato Perez RIBAS 2024 IEEE 15th Latin America Symposium on Circuits and Systems (LASCAS) DOI 10.1109/lascas60203.2024.10506169 ISBN 9798350381221	PS Electrical and Electronic Engineering
2024	Artigo em periódico	A Survey of Approximate Triple Modular Redundancy Ammes GABRIEL; Butzen Paulo FRANCISCO; André Inácio REIS; Renato Perez RIBAS JICS. JOURNAL OF INTEGRATED CIRCUITS AND SYSTEMS (ED. PORTUGUÊS) DOI 10.29292/jics.v19i3.970 ISSN 1872-0234	PS Electrical and Electronic Engineering
2023	Trabalho em evento	Evaluation of Digital Circuit Design by Combining Two - and Multi-Level Approximate Logic Synthesis Ammes GABRIEL; Butzen Paulo F; Reis André I; Renato Perez RIBAS 2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) DOI 10.1109/isvlsi59464.2023.10238642 ISBN 9798350327694	PS Hardware and Architecture
2023	Trabalho em evento	ATMR design by construction based on two-level ALS Ammes GABRIEL; Manske Guilherme B; Butzen Paulo F; Reis André I; Renato Perez RIBAS 2023 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) DOI 10.1109/sbcci60457.2023.10261973 ISBN 9798350318340	PS Hardware and Architecture
2022	Artigo em periódico	A Two-Level Approximate Logic Synthesis Combining Cube Insertion and Removal Ammes GABRIEL; Neto Walter LAU; Butzen PAULO; Gaillardon Pierre EMMANUEL; Renato Perez RIBAS IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS DOI 10.1109/tcad.2022.3143489 ISSN 0278-0070	PS Computer Graphics and Computer-Aided Design
2022	Artigo em periódico	Two-Level and Multilevel Approximate Logic Synthesis Ammes GABRIEL; Butzen Paulo FRANCISCO; André Inácio REIS; Renato Perez RIBAS JICS. JOURNAL OF INTEGRATED CIRCUITS AND SYSTEMS (ED. PORTUGUÊS) DOI 10.29292/jics.v17i3.661 ISSN 1872-0234	PS Computer Science (miscellaneous)
2021	Artigo em periódico	Logic Synthesis for Emerging Technologies Neutzling AUGUSTO; Renato Perez RIBAS JICS. JOURNAL OF INTEGRATED CIRCUITS AND SYSTEMS (ED. PORTUGUÊS) DOI 10.29292/jics.v16i1.484 ISSN 1872-0234	PS Computer Science Applications
2020	Livro	21 jogos abstratos e de estratégia no mesmo tabuleiro Renato Perez RIBAS — ISBN 6586623170	PS Mathematics (miscellaneous)
2019	Artigo em periódico	Maj-n Logic Synthesis for Emerging Technology Neutzling AUGUSTO; Marranghello Felipe S; Matos Jody MAICK; Reis ANDRE; Renato Perez RIBAS IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS DOI 10.1109/tcad.2019.2897704 ISSN 0278-0070	PS Computational Theory and Mathematics
2019	Artigo em periódico	Four-Level Forms for Memristive Material Implication Logic Marranghello Felipe S; Callegaro VINICIUS; Reis Andre I; Renato Perez RIBAS IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS DOI 10.1109/tvlsi.2019.2890843 ISSN 1063-8210	PS Hardware and Architecture
2019	Artigo em periódico	Parallel Combinational Equivalence Checking Possani Vinicius N; Mishchenko ALAN; Renato Perez RIBAS; Reis Andre I IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS DOI 10.1109/tcad.2019.2946254 ISSN 0278-0070	PS Computer Graphics and Computer-Aided Design
2019	Artigo em periódico	Exact Benchmark Circuits for Logic Synthesis Neto Walter LAU; Possani Vinicius N; Marranghello Felipe S; Matos Jody M; Gaillardon Pierre EMMANUEL et al IEEE Design & Test DOI 10.1109/mdat.2019.2952348 ISSN 2168-2356	PS Computational Theory and Mathematics
2018	Trabalho em evento	Unlocking fine-grain parallelism for AIG rewriting Possani VINICIUS; Lu Yi SHAN; Mishchenko ALAN; Pingali KESHAV; Renato Perez RIBAS et al the International Conference DOI 10.1145/3240765.3240861 ISBN 9781450359504	PS Artificial Intelligence
2018	Trabalho em evento	Exact Multi-Level Benchmark Circuit Generation for Logic Synthesis Evaluation Neto Walter L; Possani Vinicius N; Marranghello Felipe S; Matos Jody M; Reis Andre I et al 2018 31st Symposium on Integrated Circuits and Systems Design (SBCCI) DOI 10.1109/sbcci.2018.8533248 ISBN 9781538674314	PS Hardware and Architecture
2018	Trabalho em evento	Exact Multi-Level Logic Benchmark Generation Walter Lau NETO; Felipe S MARRANGHELLO; Vinicius N POSSANI; Andre Inacio REIS; Renato Perez RIBAS International Workshop on Logic and Synthesis (IWLS)	PS Logic
2018	Trabalho em evento	Parallel AIG Rewriting Vinicius N POSSANI; Y LU; Alan MISHCHENKO; K PINGALI; Renato Perez RIBAS et al International Workshop on Logic & Synthesis (IWLS)	PS Theoretical Computer Science
2018	Trabalho em evento	Jogos Lógicos de Tabuleiro como Instrumento Pedagógico de Socialização e Emancipação Renato Perez RIBAS; Viviane Dulis De LIMA; Aline Guterres FERREIRA; Nilseia Lapresa RIBAS Congresso Brasileiro de Extensão Universitária	SH Education
2018	Artigo em periódico	Effective Logic Synthesis for Threshold Logic Circuit Design Neutzling AUGUSTO; Matos Jody MAICK; Mishchenko ALAN; Reis ANDRE; Renato Perez RIBAS IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS DOI 10.1109/tcad.2018.2834434 ISSN 0278-0070	PS Computer Graphics and Computer-Aided Design
2017	Trabalho em evento	Binary adder circuit design using emerging MIGFET devices Baqueta Jeferson J; Marranghello Felipe S; Possani Vinicius N; Neutzling AUGUSTO; Reis Andre I et al 2017 18th International Symposium on Quality Electronic Design (ISQED) DOI 10.1109/isqed.2017.7918304 ISBN 9781509054046	PS Electrical and Electronic Engineering
2017	Artigo em periódico	A Simple and Effective Heuristic Method for Threshold Logic Identification Neutzling AUGUSTO; Martins Mayler G A; Callegaro VINICIUS; Reis Andri I; Renato Perez RIBAS IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS DOI 10.1109/tcad.2017.2729403 ISSN 0278-0070	PS Computer Science Applications
2017	Artigo em periódico	SAT-Based Formulation for Logical Capacity Evaluation of VIA-Configurable Structured ASIC Dal Bem VINICIUS; Marranghello FELIPE; Reis ANDRE; Renato Perez RIBAS IEEE Transactions on Emerging Topics in Computing DOI 10.1109/tetc.2016.2644381 ISSN 2168-6750	PS Computer Science Applications
2017	Artigo em periódico	Formação de Professores nos Jogos Lógicos de Tabuleiro Liliane Ferrari GIORDANI; Renato Perez RIBAS EXPRESSA EXTENSÃO DOI 10.15210/ee.v21i2.7869 ISSN 2358-8195	SH Education
2016	Trabalho em evento	Performance evaluation of optimized transistor networks built using independent-gate FinFET Valdes Andres M A; Possani VINICIUS; Marranghello Felipe S; Reis Andre I; Renato Perez RIBAS 2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS) DOI 10.1109/lascas.2016.7451051 ISBN 9781467378352	PS Electrical and Electronic Engineering
2016	Trabalho em evento	On-silicon validation of a benchmark generation methodology for effectively evaluating combinational cell library design De Carvalho M; Maurício ALTIERI; Lauro PURICELLI; Paulo BUTZEN; Renato Perez RIBAS et al 2016 17th LatinAmerican Test Symposium (LATS) DOI 10.1109/latw.2016.7483353 ISBN 9781509013319	PS Industrial and Manufacturing Engineering

2025 Livro

PS Discrete Mathematics and Combinatorics

Divirta-se com 21 jogos lógicos no mesmo tabuleiro: Volume 1

—

Renato Perez RIBAS

ISBN 9786561440547

2024 Trabalho em evento

PS Electrical and Electronic Engineering

Extending Multilevel ALS to Design ATMRs

2024 IEEE 15th Latin America Symposium on Circuits and Systems (LASCAS)

Ammes GABRIEL; Manske Guilherme B; Butzen Paulo F; Reis André I; Renato Perez RIBAS

DOI ISBN 9798350381221

2024 Artigo em periódico

PS Electrical and Electronic Engineering

A Survey of Approximate Triple Modular Redundancy

JICS. JOURNAL OF INTEGRATED CIRCUITS AND SYSTEMS (ED. PORTUGUÊS)

Ammes GABRIEL; Butzen Paulo FRANCISCO; André Inácio REIS; Renato Perez RIBAS

DOI ISSN 1872-0234

2023 Trabalho em evento

PS Hardware and Architecture

Evaluation of Digital Circuit Design by Combining Two - and Multi-Level Approximate Logic Synthesis

2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

Ammes GABRIEL; Butzen Paulo F; Reis André I; Renato Perez RIBAS

DOI ISBN 9798350327694

2023 Trabalho em evento

PS Hardware and Architecture

ATMR design by construction based on two-level ALS

2023 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)

Ammes GABRIEL; Manske Guilherme B; Butzen Paulo F; Reis André I; Renato Perez RIBAS

DOI ISBN 9798350318340

2022 Artigo em periódico

PS Computer Graphics and Computer-Aided Design

A Two-Level Approximate Logic Synthesis Combining Cube Insertion and Removal

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS

Ammes GABRIEL; Neto Walter LAU; Butzen PAULO; Gaillardon Pierre EMMANUEL; Renato Perez RIBAS

DOI ISSN 0278-0070

2022 Artigo em periódico

PS Computer Science (miscellaneous)

Two-Level and Multilevel Approximate Logic Synthesis

JICS. JOURNAL OF INTEGRATED CIRCUITS AND SYSTEMS (ED. PORTUGUÊS)

Ammes GABRIEL; Butzen Paulo FRANCISCO; André Inácio REIS; Renato Perez RIBAS

DOI ISSN 1872-0234

2021 Artigo em periódico

PS Computer Science Applications

Logic Synthesis for Emerging Technologies

JICS. JOURNAL OF INTEGRATED CIRCUITS AND SYSTEMS (ED. PORTUGUÊS)

Neutzling AUGUSTO; Renato Perez RIBAS

DOI ISSN 1872-0234

2020 Livro

PS Mathematics (miscellaneous)

21 jogos abstratos e de estratégia no mesmo tabuleiro

—

Renato Perez RIBAS

ISBN 6586623170

2019 Artigo em periódico

PS Computational Theory and Mathematics

Maj-n Logic Synthesis for Emerging Technology

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS

Neutzling AUGUSTO; Marranghello Felipe S; Matos Jody MAICK; Reis ANDRE; Renato Perez RIBAS

DOI ISSN 0278-0070

2019 Artigo em periódico

PS Hardware and Architecture

Four-Level Forms for Memristive Material Implication Logic

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Marranghello Felipe S; Callegaro VINICIUS; Reis Andre I; Renato Perez RIBAS

DOI ISSN 1063-8210

2019 Artigo em periódico

PS Computer Graphics and Computer-Aided Design

Parallel Combinational Equivalence Checking

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS

Possani Vinicius N; Mishchenko ALAN; Renato Perez RIBAS; Reis Andre I

DOI ISSN 0278-0070

2019 Artigo em periódico

PS Computational Theory and Mathematics

Exact Benchmark Circuits for Logic Synthesis

IEEE Design & Test

Neto Walter LAU; Possani Vinicius N; Marranghello Felipe S; Matos Jody M; Gaillardon Pierre EMMANUEL et al

DOI ISSN 2168-2356

2018 Trabalho em evento

PS Artificial Intelligence

Unlocking fine-grain parallelism for AIG rewriting

the International Conference

Possani VINICIUS; Lu Yi SHAN; Mishchenko ALAN; Pingali KESHAV; Renato Perez RIBAS et al

DOI ISBN 9781450359504

2018 Trabalho em evento

PS Hardware and Architecture

Exact Multi-Level Benchmark Circuit Generation for Logic Synthesis Evaluation

2018 31st Symposium on Integrated Circuits and Systems Design (SBCCI)

Neto Walter L; Possani Vinicius N; Marranghello Felipe S; Matos Jody M; Reis Andre I et al

DOI ISBN 9781538674314

2018 Trabalho em evento

PS Logic

Exact Multi-Level Logic Benchmark Generation

International Workshop on Logic and Synthesis (IWLS)

Walter Lau NETO; Felipe S MARRANGHELLO; Vinicius N POSSANI; Andre Inacio REIS; Renato Perez RIBAS

2018 Trabalho em evento

PS Theoretical Computer Science

Parallel AIG Rewriting

International Workshop on Logic & Synthesis (IWLS)

Vinicius N POSSANI; Y LU; Alan MISHCHENKO; K PINGALI; Renato Perez RIBAS et al

2018 Trabalho em evento

SH Education

Jogos Lógicos de Tabuleiro como Instrumento Pedagógico de Socialização e Emancipação

Congresso Brasileiro de Extensão Universitária

Renato Perez RIBAS; Viviane Dulis De LIMA; Aline Guterres FERREIRA; Nilseia Lapresa RIBAS

2018 Artigo em periódico

PS Computer Graphics and Computer-Aided Design

Effective Logic Synthesis for Threshold Logic Circuit Design

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS

Neutzling AUGUSTO; Matos Jody MAICK; Mishchenko ALAN; Reis ANDRE; Renato Perez RIBAS

DOI ISSN 0278-0070

2017 Trabalho em evento

PS Electrical and Electronic Engineering

Binary adder circuit design using emerging MIGFET devices

2017 18th International Symposium on Quality Electronic Design (ISQED)

Baqueta Jeferson J; Marranghello Felipe S; Possani Vinicius N; Neutzling AUGUSTO; Reis Andre I et al

DOI ISBN 9781509054046

2017 Artigo em periódico

PS Computer Science Applications

A Simple and Effective Heuristic Method for Threshold Logic Identification

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS

Neutzling AUGUSTO; Martins Mayler G A; Callegaro VINICIUS; Reis Andri I; Renato Perez RIBAS

DOI ISSN 0278-0070

2017 Artigo em periódico

PS Computer Science Applications

SAT-Based Formulation for Logical Capacity Evaluation of VIA-Configurable Structured ASIC

IEEE Transactions on Emerging Topics in Computing

Dal Bem VINICIUS; Marranghello FELIPE; Reis ANDRE; Renato Perez RIBAS

DOI ISSN 2168-6750

2017 Artigo em periódico

SH Education

Formação de Professores nos Jogos Lógicos de Tabuleiro

EXPRESSA EXTENSÃO

Liliane Ferrari GIORDANI; Renato Perez RIBAS

DOI ISSN 2358-8195

2016 Trabalho em evento

PS Electrical and Electronic Engineering

Performance evaluation of optimized transistor networks built using independent-gate FinFET

2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)

Valdes Andres M A; Possani VINICIUS; Marranghello Felipe S; Reis Andre I; Renato Perez RIBAS

DOI ISBN 9781467378352

2016 Trabalho em evento

PS Industrial and Manufacturing Engineering

On-silicon validation of a benchmark generation methodology for effectively evaluating combinational cell library design

2016 17th LatinAmerican Test Symposium (LATS)

De Carvalho M; Maurício ALTIERI; Lauro PURICELLI; Paulo BUTZEN; Renato Perez RIBAS et al

DOI ISBN 9781509013319